1. Field of the Invention
The present invention generally relates to integrated circuits planarization processes, and more particularly to a chemical mechanical polishing (CMP) process for semiconductor wafers that provides avoid microscratches.
2. Description of the Prior Art
The fabrication of integrated circuits on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic photomasks onto the wafer. The photomasking processing steps opens selected areas to be exposed on the wafer for subsequent processes such as inclusion of impurities, oxidation, or etching.
During the forming of integrated circuit structures, it has become increasingly important to provide structures having multiple metallization layers due to the continuing miniaturization of the circuit elements in the structure. Each of the metal layers is typically separated from another metal layer by an insulation layer, such as an oxide layer. To enhance the quality of an overlying metallization layer, one without discontinuities of other blemishes, it is imperative to provide an underlying surface for the metallization layer that is ideally planar. The process of planarization is necessary and desirable to facilitate masking and etching operations. Planarization of metal interconnect layers improves the yield of devices contained in the device array of a wafer, and the reliability of such devices. Planarization produces a constant thickness across the circuit of a die, minimizes the presence of cavities, and allows metal interconnect lines to be continuous, where they would otherwise be discontinuous over a non-planar surface containing cavities.
Planarization of integrated circuit devices is necessary and desirable to facilitate masking and etching operations. A planarized surface provides a constant depth of focus across the surface of a die for exposing patterns in a photolithography emulsion. While complete planarization is desirable, it is difficult to achieve as the topology of integrated circuit varies across the surface of a die on a wafer.
Integrated circuits are manufactured by stacking multiple layers of metal, semiconductor, and dielectric materials on a top surface of a semiconductor substrate. Each of these layers may be patterned to create complex microelectronic circuitry. Planarization of each of the layers is an important limitation to the number of layers used to form the integrated circuit devices. Non-planar layers are difficult to pattern using conventional photo resist techniques because the focal length varies across the surface of the semiconductor wafer. It is also difficult to form subsequent films on top of a non-planar layer resulting in voids in the subsequent layer. Also, non-planar layers are difficult to completely remove during an etch process. A number of planarization processes have been developed and include chemical mechanical polishing.
The chemical mechanical polishing process involves holding a thin wafer of semiconductor material against a rotating wetted polish pad surface under a controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution is used as a chemical etch component in combination with an abrasive material such as aluminum or silica particles. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft, porous wetted pad material such as blown polyurethane.
In the conventional DRAM process, transistors 20, 21, a contact 30, and capacitors 40 are formed on a substrate 10, wherein the transistors 20-1, 20-2, 20-3, 20-4, 20-5, a contact 30 and capacitors 40 are components of memory array as shown in part B of FIG. 1. Transistors 21-1, 21-2 are used to control and access data in memory array as shown in part A of FIG. 1. An interlevel dielectric layer 50 is deposited on the memory array B, logic device A and the substrate 10, wherein surface of the interlevel dielectric layer 50 has step height difference between the memory array B and the logic device A. Photoresist layer 60 is formed on a portion of the interlevel dielectric layer 50 over the logic device A by using lithographic process. The interlevel dielectric layer 50 is etched by using the photoresist layer 50 as a mask. Then, a sidewall 70 and a corner 80 are formed in the interlevel dielectric layer 50 between the memory array B and the logic device A at the etching step as shown in FIG. 2. The polishing slurry 90 will pile up around the corner 80, when performing chemical mechanical polishing process. A polishing slurry 90 such as a mixture of either a basic or acidic solution is used as a chemical etch component in combination with an abrasive material such as aluminum or silica particles. They will over polished the interlevel dielectric layer 50, become concave 95 around the corner 80, as shown in FIG. 3, and then cause yield loss and surface contamination.
In accordance with the present invention, it is a main object of this invention to form a smooth corner of interlevel dielectric layer in a DRAM.
It is another object of this invention that smooth corner is very desirable in the chemical mechanical polishing process avoided microstratch.
This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.